By Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis
This ebook describes new and potent methodologies for modeling, reading and mitigating cell-internal sign electromigration in nanoCMOS, with major circuit lifetime advancements and no effect on functionality, sector and gear. The authors are the 1st to research and suggest an answer for the electromigration results within common sense cells of a circuit. They express during this ebook that an interconnect within a telephone can fail lowering significantly the circuit lifetime they usually reveal a strategy to optimize the life of circuits, by way of putting the output, Vdd and Vss pin of the cells within the much less serious areas, the place the electromigration results are decreased. Readers might be enabled to use this technique just for the serious cells within the circuit, fending off impression within the circuit hold up, region and function, hence expanding the life of the circuit with out loss in different features.
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Additional resources for Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
2013a). 19 20 2 State of the Art Fig. 2 Mitigating the EM Effects in Different Types of Interconnections Electromigration (EM) is an aging effect taking place in interconnect wires, contacts, and vias in an integrated circuit (Tu 2003). Most works in the literature are considering the different net classes to mitigate the EM effects: TSVs (present in 3D circuits), power supply network, clock network, and vias, as Fig. 8 presents, but few works told about the EM in the signal interconnects within a standard cell (internal-cell EM) that is the focus of this work.
If frequency Ä Fmax obtained from the flow in Fig. 7, then exit. 1 Mitigating the EM Effects in Different IC Design Flow Stages Fig. 6 Per-net NDRs flow to fix EM Irms violations (Kahng et al. 2013a) Fig. 7 Automated flow to determine Fmax (Kahng et al. 2013a). 19 20 2 State of the Art Fig. 2 Mitigating the EM Effects in Different Types of Interconnections Electromigration (EM) is an aging effect taking place in interconnect wires, contacts, and vias in an integrated circuit (Tu 2003). Most works in the literature are considering the different net classes to mitigate the EM effects: TSVs (present in 3D circuits), power supply network, clock network, and vias, as Fig.
2013). A transient power integrity analysis flow for lifetime prediction is developed, which integrates the EM modeling approach. Pak et al. (2013) model the EM on TSVs and local vias used together for vertical power delivery. Cheng et al. (2013) propose a framework at architecture level to alleviate EM effects of defective TSVs. At first, the relationship between various TSV defects and EM induced TSV mean time to failure (MTTF) degradation is analyzed. Then, a framework to protect defective TSVs and improve EM MTTF by balancing their current flow directions is proposed.