By G.H. Müller, G. Takeuti, T. Tugue
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Extra info for Logic Symposia, Hakone, 1979, 1980
33 Measured waveforms of the Type‐B backup flip‐flop during operation. 34 Evaluation program of alternating active and sleep modes. 35 Evaluation results of power reduction. 36 (a) Circuit diagram and (b) power‐gating sequence of the CAAC‐IGZO SRAM. 37 Mask layout and layer structure of the CAAC‐IGZO SRAM. 38 Estimation of the BET. 39 Static noise margins of CAAC‐IGZO SRAM and standard SRAM during read (a), write (b), and hold (c) operations. 36(a). 42 Block diagram of 32‐kbit CAAC‐IGZO SRAM. 44 Waveforms measured in power gating.
29 Layout of simulated FF with a hybrid process of 45‐nm Si and 180‐nm CAAC‐IGZO FETs. 30 Micrograph of the 32‐bit normally‐off CPU (ARM® Cortex®‐M0). 31 Cross‐sectional view of SRAM formed by a hybrid process of 180‐nm Si and 60‐nm CAAC‐IGZO FETs. 32 Block diagram of the 32‐bit normally‐off CPU (ARM® Cortex®‐M0). 33 Measured waveforms of the Type‐B backup flip‐flop during operation. 34 Evaluation program of alternating active and sleep modes. 35 Evaluation results of power reduction. 36 (a) Circuit diagram and (b) power‐gating sequence of the CAAC‐IGZO SRAM.
Fujita, Masahiro, 1956– author. Title: Physics and technology of crystalline oxide semiconductor CAAC-IGZO. Application to LSI / Shunpei Yamazaki, Masahiro Fujita. Description: Chichester, West Sussex, United Kingdom : John Wiley & Sons, Ltd Registered office John Wiley & Sons Ltd,  | Includes bibliographical references and index. Identifiers: LCCN 2016025860 | ISBN 9781119247340 (cloth) | ISBN 9781119247432 (epub) | ISBN 9781119247425 (Adobe PDF) Subjects: LCSH: Semiconductors–Materials.