By Shunpei Yamazaki, Masahiro Fujita

This e-book describes the appliance of c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) expertise in large-scale integration (LSI) circuits. The functions contain Non-volatile Oxide Semiconductor Random entry reminiscence (NOSRAM), Dynamic Oxide Semiconductor Random entry reminiscence (DOSRAM), critical processing unit (CPU), field-programmable gate array (FPGA), photo sensors, and and so forth. The ebook additionally covers the gadget physics (e.g., off-state features) of the CAAC-IGZO box impact transistors (FETs) and method know-how for a hybrid constitution of CAAC-IGZO and Si FETs. It explains an incredibly low off-state present know-how used in the LSI circuits, demonstrating lowered energy intake in LSI prototypes fabricated by way of the hybrid procedure. one more books within the sequence will describe the basics; and the categorical software of CAAC-IGZO to liquid crystal display and OLED screens.

Key positive factors:

• Outlines the physics and features of CAAC-IGZO FETs that give a contribution to favorable operations of LSI units.
• Explains the appliance of CAAC-IGZO to LSI units, highlighting attributes together with low off-state present, low strength intake, and perfect cost retention.
• Describes the NOSRAM, DOSRAM, CPU, FPGA, snapshot sensors, and etc., bearing on prototype chips fabricated by means of a hybrid means of CAAC-IGZO and Si FETs.

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Extra info for Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO : Application to LSI

Example text

33 Measured waveforms of the Type‐B backup flip‐flop during operation. 34 Evaluation program of alternating active and sleep modes. 35 Evaluation results of power reduction. 36 (a) Circuit diagram and (b) power‐gating sequence of the CAAC‐IGZO SRAM. 37 Mask layout and layer structure of the CAAC‐IGZO SRAM. 38 Estimation of the BET. 39 Static noise margins of CAAC‐IGZO SRAM and standard SRAM during read (a), write (b), and hold (c) operations. 36(a). 42 Block diagram of 32‐kbit CAAC‐IGZO SRAM. 44 Waveforms measured in power gating.

29 Layout of simulated FF with a hybrid process of 45‐nm Si and 180‐nm CAAC‐IGZO FETs. 30 Micrograph of the 32‐bit normally‐off CPU (ARM® Cortex®‐M0). 31 Cross‐sectional view of SRAM formed by a hybrid process of 180‐nm Si and 60‐nm CAAC‐IGZO FETs. 32 Block diagram of the 32‐bit normally‐off CPU (ARM® Cortex®‐M0). 33 Measured waveforms of the Type‐B backup flip‐flop during operation. 34 Evaluation program of alternating active and sleep modes. 35 Evaluation results of power reduction. 36 (a) Circuit diagram and (b) power‐gating sequence of the CAAC‐IGZO SRAM.

Fujita, Masahiro, 1956– author. Title: Physics and technology of crystalline oxide semiconductor CAAC-IGZO. Application to LSI / Shunpei Yamazaki, Masahiro Fujita. Description: Chichester, West Sussex, United Kingdom : John Wiley & Sons, Ltd Registered office John Wiley & Sons Ltd, [2017] | Includes bibliographical references and index. Identifiers: LCCN 2016025860 | ISBN 9781119247340 (cloth) | ISBN 9781119247432 (epub) | ISBN 9781119247425 (Adobe PDF) Subjects: LCSH: Semiconductors–Materials.

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